View EM78P153E_1875484.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 1 1 . general description EM78P153E is an 8 - bit microprocessor with low - power and high - speed cmos technology. it is equipped with a 512*13 - bits electrical one time programmable read only memory (otp - rom). it provides a protection bit to prevent intrusion of u ser?s code in the otp memory as well as 15 option bits to match user?s requirements. with its otp - rom feature, the EM78P153E offers users a convenient way of developing and verifying their programs. moreover, user developed code can be easily programmed w ith the emc writer.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 2 2 . features ? 14 - lead packages : EM78P153E ? operating voltage range : 2.3v~5.5v ? available in temperature range: 0 c~70 c ? operating frequency rang (base on 2 clocks ): * crystal mode: dc~20mhz at 5v, dc~8mhz at 3v, dc~4mhz at 2.3v. * erc mode: dc~4mhz at 5v, dc~4mhz at 3v, dc~4mhz at 2.3v. ? low power consumption: * less then 1.5ma at 5v/4mhz * typical of 15 m a, at 3v/32khz * typical of 1 m a, during the sleep mode ? 512 13 bits on chip rom ? three built - in calibrated irc oscillat ors ? programmable prescaler of oscillator set - up time ? on - board bit by bit programming ? one security register to prevent the code in the otp memory from intruding ? one configuration register to match the user?s requirements ? 32 8 bits on chip regist ers (sram, general purpose register) ? 2 bi - directional i/o ports ? 5 level stacks for subroutine nesting ? 8 - bit real time clock/counter (tcc) with selective signal sources, trigger edges, and overflow interrupt ? power down mode (sleep mode) ? three avai lable interruptions * tcc overflow interrupt * input - port status changed interrupt (wake up from the sleep mode) * external interrupt ? programmable free running watchdog timer ? 7 programmable pull - high i/o pins ? 7 programmable open - drain i/o pins ? 6 pr ogrammable pull - down i/o pins ? two clocks per instruction cycle ? 99.9% single instruction cycle commands
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 3 ? package types: * 14 pin dip 300mil: EM78P153Ep * 14 pin sop 150mil: EM78P153En ? the transient point of system frequency between hxt and lxt is ar ound 400khz.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 4 3 . pin assignments 1 2 3 4 5 8 9 1 0 EM78P153E 6 7 11 12 13 14 p50 p67 p66 vdd p65/osci p64/osco p63//rst p51 p52 p53 vss p60//int p61 p62/tcc fig. 1 pin assignment table 1 pin description symbol pin no. type function vdd 4 - power supply. p65/osci 5 i/o * general purpose i/o pin. * externa l clock signal input. * input pin of xt oscillator. * pull_high/open - drain * wake up from sleep mode when the status of the pin changes. p64/osco 6 i/o * general purpose i/o pin. * external clock signal input. * input pin of xt oscillator. * pull_high/ope n - drain * wake up from sleep mode when the status of the pin changes. p63/reset 7 i * if set as /reset and remain at logic low, the device will be under reset. * if p63 is set and kept at logic ?high,? the oscillator will oscillate. * if kept at logic lo w, it cannot oscillate. * wake up from sleep mode when the status of the pin changes. * voltage on /reset must not exceed vdd during the normal mode. * pull_high is on if defined as /reset. * p63 is input pin only p62/tcc 8 i/o * general purpose i/o pin. * pull_high/open_drain/pull_down. * wake up from sleep mode when the status of the pin changes. * external timer/counter input. p61 9 i/o * general purpose i/o pin. * pull_high/open_drain/pull_down. * wake up from sleep mode when the status of the pin cha nges. * schmitt trigger input during programming mode p60//int 10 i/o * general purpose i/o pin. * pull_high/open_drain/pull_down.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 5 * wake up from sleep mode when the status of the pin changes. * schmitt trigger input during the programming mode. * exter nal interrupt pin triggered by falling edge. p66, p67 2, 3 i/o * general purpose i/o pin. * pull - high/open - drain. * wake up from sleep mode when the status of the pin changes. p50~p52 1,14,13 i/o * general purpose i/o pin. * pull - down p53 12 i/o * gener al purpose i/o pin. vss 11 - * ground.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 6 4 . function description interrupt controller rom instruction register instruction decoder r2 alu stack acc r3 r3 oscillator/timing control wdt timer prescaler r1(tcc) ram data & control bus osci osco /reset tcc /int i/o port 6 ioc6 r6 built-in osc p60 p61 p62/tcc p63/rest p64/osco p65/osci p66 p67 fig. 2 function block diagram 4 .1 operational registers 1. r0 (indirect addressing register) r0 is not a physically implemented register. i ts major function is to be an indirect addressing pointer. any instruction using r0 as a pointer, actually accesses data pointed by the ram select register (r4). 2. r1 (time clock /counter) ? increased by an external signal edge, which is defined by te bit (cont - 4) through the tcc pin, or by the instruction cycle clock. ? writable and readable as any other registers. ? defined by resetting pab(cont - 3). ? the prescaler is assigned to tcc if the pab bit (cont - 3) is reset. ? the contents of the prescaler count er is cleared only when a value is written to tcc register.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 7 3. r2 (program counter) & stack ? depending on the device type, r2 and hardware stack are 9 - bit wide. the structure is depicted in fig.3. ? 512 13 bits on - chip otp rom addresses to the relative p rogramming instruction codes. one program page is 512 words long. ? r2 is set as all "0"s when under reset condition. ? "jmp" instruction allows direct loading of the lower 9 program counter bits. thus, "jmp" allows pc to go to any location within a page. ? "call" instruction loads the lower 9 bits of the pc, and then pc+1 is pushed into the stack. thus, the subroutine entry address can be located anywhere within a page. ? "ret" ("retl k", "reti") instruction loads the program counter with the contents of t he top - level stack. ? "add r2,a" allows the contents of ?a? to be added to the current pc, and the ninth of the pc are cleared. ? "mov r2,a" allows to load an address from the "a" register to the lower 8 bits of the pc, and the ninth bits of the pc are cle ared. ? any instruction that is written to r2 (e.g. "add r2,a", "mov r2,a", "bc r2,6", ) will cause the ninth bits (a8) of the pc to be cleared. thus, the computed jump is limited to the first 256 locations of a page. ? all instructions are single inst ruction cycle (fclk/2 or fclk/4), except for the instruction that would change the contents of r2. this instruction will need one more instruction cycle. pc 0 0 a8 a7 ~ a0 call ret retl retl k stack 1 stack 2 stack 3 stack 4 stack 5 000 1ff page 0 00 fig. 3 program counter organization
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 8 r0 r1(tcc) r2(pc) r3(status) r4(rsr) r5(port5) r6(port6) rf r10 . . . . general registers r2f stack (5 levels) ioc5 ioc6 iocb iocc iocd ioce iocf cont 00 01 02 04 03 05 06 0b 0c 0d 0e 0f fig. 4 data memory configuration
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 9 4. r3 (status register) 7 6 5 4 3 2 1 0 rst gp1 gp0 t p z dc c ? bit 0 (c) carry flag ? bit 1 (dc) auxiliary carry flag ? bit 2 (z) zero flag. set to "1" if the result of an arithmetic o r logic operation is zero. ? bit 3 (p) power down bit. set to 1 during power on or by a "wdtc" command and reset to 0 by a "slep" command. ? bit 4 (t) time - out bit. set to 1 with the "slep" and "wdtc" command, or during power up and reset to 0 by wdt time - out. ? bit5 ~ 6 (gp0 ~ 1) general - purpose read/write bits. ? bit 7 (rst) bit for reset type. set to 1 if wake - up from sleep mode on pin change. set to 0 if wake - up from other reset types 5. r4 (ram select register) ? bits 0~5 are used to select registers ( address: 00~06, 0f~2f) in the indirect addressing mode. ? bits 6~7 are general - purpose read/write bits. ? see the configuration of the data memory in fig. 4. 6. r5 ~ r6 (port 5 ~ port 6) ? r5 and r6 are i/o registers. ? only the lower 4 bits of r5 are avai lable. ? the upper 4 bits of r5 are fixed to 0. ? p63 is input only. 7. rf (interrupt status register) 7 6 5 4 3 2 1 0 - - - - - exif icif tcif ?1? means interrupt request, and ?0? means no interrupt occurs. ? bit 0 (tcif) tcc overflowing interrupt fla g. set when tcc overflows, reset by software. ? bit 1 (icif) port 6 input status changed interrupt flag. set when port 6 input changes, reset by software. ? bit 2 (exif) external interrupt flag. set by falling edge on /int pin, reset by software.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 10 ? bits 3 ~ 7 not used. ? rf can be cleared by instruction but cannot be set. ? iocf is the interrupt mask register. ? note that the result of reading rf is the "logic and" of rf and iocf. 8. r10 ~ r2f ? all of these are the 8 - bit general - purpose registers. 4 .2 spec ial purpose registers 1. a (accumulator) ? internal data transfer, or instruction operand holding ? it can not be addressed. 2. cont (control register) 7 6 5 4 3 2 1 0 - /int ts te pab psr2 psr1 psr0 ? bit 0 (psr0) ~ bit 2 (psr2) tcc/wdt prescaler bits. psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 ? bit 3 (pab) prescaler assignment bit. 0: tcc 1: wdt ? bit 4 (te) tcc signal edge 0: inc rement if the transition from low to high takes place on tcc pin 1: increment if the transition from high to low takes place on tcc pin ? bit 5 (ts) tcc signal source 0: internal instruction cycle clock 1: transition on tcc pin when ts is 1, the r62 i/o c ontrol bit will set to 1; otherwise, it will be the value defined by user. ? bit 6 (int) interrupt enable flag 0: masked by disi or hardware interrupt
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 11 1: enabled by eni/reti instructions ? bit 7 not used. ? cont register is both readable and writable. 3. ioc5 ~ ioc6 (i/o port control register) ? "1" put the relative i/o pin into high impedance, while "0" defines the relative i/o pin as output. ? only the lower 4 bits of ioc5 are available to be defined. ? ioc5 and ioc6 registers are both readable and writ able. 4. iocb (pull - down control register) 7 6 5 4 3 2 1 0 - /pd6 /pd5 /pd4 - /pd2 /pd1 /pd0 ? bit 0 (/pd0) control bit is used to enable the pull - down of p50 pin. 0: enable internal pull - down 1: disable internal pull - down ? bit 1 (/pd1) control bit is u sed to enable the pull - down of p51 pin. ? bit 2 (/pd2) control bit is used to enable the pull - down of p52 pin. ? bit 3 not used. ? bit 4 (/pd4) control bit is used to enable the pull - down of p60 pin. ? bit 5 (/pd5) control bit is used to enable the p ull - down of p61 pin. ? bit 6 (/pd6) control bit is used to enable the pull - down of p62 pin. ? bit 7 not used. ? iocb register is both readable and writable. 5. iocc (open - drain control register) 7 6 5 4 3 2 1 0 od7 od6 od5 od4 - od2 od1 od0 ? bit 0 (od0) control bit is used to enable the open - drain of p60 pin. 0: disable open - drain output 1: enable open - drain output ? bit 1 (od1) control bit is used to enable the open - drain of p61 pin. ? bit 2 (od2) control bit is used to enable the open - drain of p6 2 pin. ? bit 3 not used. ? bit 4 (od4) control bit is used to enable the open - drain of p64 pin. ? bit 5 (od5) control bit is used to enable the open - drain of p65 pin. ? bit 6 (od6) control bit is used to enable the open - drain of p66 pin. ? bit 7 (od7) control bit is used to enable the open - drain of p67 pin.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 12 ? iocc register is both readable and writable. 6. iocd (pull - high control register) 7 6 5 4 3 2 1 0 /ph7 /ph6 /ph5 /ph4 - /ph2 /ph1 /ph0 ? bit 0 (/ph0) control bit used to enable the pull - high of p60 pin. 0: enable internal pull - high 1: disable internal pull - high ? bit 1 (/ph1) control bit is used to enable the pull - high of p61 pin. ? bit 2 (/ph2) control bit is used to enable the pull - high of p62 pin. ? bit 3 not used. ? bit 4 (/ph4) control bit is used to enable the pull - high of p64 pin. ? bit 5 (/ph5) control bit is used to enable the pull - high of p65 pin. ? bit 6 (/ph6) control bit is used to enable the pull - high of p66 pin. ? bit 7 (/ph7) control bit is used to enable the pull - high of p67 pin. ? iocd register is both readable and writable. 7. ioce (wdt control register) 7 6 5 4 3 2 1 0 wdte eis - - - - - - ? bit 7 (wdte) control bit used to enable watchdog timer. 0: disable wdt. 1: enable wdt. wdte is both readable and writable. ? bit 6 ( eis) control bit is used to define the function of p60(/int) pin. 0: p60, bi - directional i/o pin. 1: /int, external interrupt pin. in this case, the i/o control bit of p60 (bit 0 of ioc6) must be set to "1". when eis is "0", the path of /int is masked. whe n eis is "1", the status of /int pin can also be read by way of reading port 6 (r6). refer to fig. 7. eis is both readable and writable. ? bits 0~5 not used. 8. iocf (interrupt mask register) 7 6 5 4 3 2 1 0 - - - - - exie icie tcie ? bit 0 (tcie) tcif i nterrupt enable bit. 0: disable tcif interrupt
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 13 1: enable tcif interrupt ? bit 1 (icie) icif interrupt enable bit. 0: disable icif interrupt 1: enable icif interrupt ? bit 2 (exie) exif interrupt enable bit. 0: disable exif interrupt 1: enable exif interrup t ? bits 3~7 not used. ? individual interrupt is enabled by setting its associated control bit in the iocf to "1". ? global interrupt is enabled by the eni instruction and is disabled by the disi instruction. refer to fig. 9. ? iocf register is both readab le and writable. 4 .3 tcc/wdt & prescaler there is an 8 - bit counter available as prescaler for the tcc or wdt. the prescaler is available for either the tcc or wdt only at any given time, and the pab bit of the cont register is used to determine the prescal er assignment. the psr0~psr2 bits determine the ratio. the prescaler is cleared each time the instruction is written to tcc under tcc mode. the wdt and prescaler, when assigned to wdt mode, are cleared by the ?wdtc? or ?slep? instructions. fig. 5 depicts t he circuit diagram of tcc/wdt. ? r1(tcc) is an 8 - bit timer/counter. the clock source of tcc can be internal or external clock input (edge selectable from tcc pin). if tcc signal source is from internal clock, tcc will increase by 1 at every instruction cyc le (without prescaler). referring to fig. 5, clk=fosc/2 or clk=fosc/4, depends on the code option bit clk. clk=fosc/2 is used if clk bit is "0", and clk=fosc/4 is used if clk bit is "1". if tcc signal source is from external clock input, tcc is increased b y 1 at every falling edge or rising edge of tcc pin. ? the watchdog timer is a free running on - chip rc oscillator. the wdt will keep running even when the oscillator driver has been turned off (i.e. in sleep mode). during normal operation or sleep mode, a wdt time - out (if enabled) will cause the device to reset. the wdt can be enabled or disabled any time during normal mode by software programming. refer to wdte bit of ioce register. without prescaler, the wdt time - out period is approximately 18 ms 1 (defaul t). 1 : vdd = 5v, set up time period = 16.5ms 5% vdd = 3v, set up time period = 18ms 5%
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 14 4 .4 i/o ports the i/o registers, both port 5 and port 6, are bi - directional tri - state i/o ports. port 6 can be pulled - high internally by software except p63. in addition, port 6 can also have open - drain output by software except p63. input status chang ed interrupt (or wake - up) function is available from port 6. p50 ~ p52 and p60 ~ p62 pins can be pulled - down by software. each i/o pin can be defined as "input" or "output" pin by the i/o control register (ioc5 ~ ioc6) except p63 . the i/o registers and i/o control registers are both readable and writable. the i/o interface circuits for port 5 and port 6 are shown in fig. 6, fig.7, and fig. 8 respectively. clk(fosc/2 or fosc/4) data bus 0 1 m u x m u x 1 0 sync 2 cycles tcc(r1) te ts pab tcc overflow interrupt pab pab 0 1 m u x tcc pin wdt wdte (in loce) mux wdt time out 8-bit counter 8-to-1 mux psr0~psr2 0 1 fig. 5 block diagram of tcc and wdt
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 15 pcwr pcrd pdwr pdrd iod 0 1 m u x port q q _ d d q q _ clk p r c l clk p r c l *pull - down is not shown in the figure. fig. 6 the circuit of i/o port and i/o control register for port 5 pcrd iod pcwr pdwr pdrd bit 6 of ioce port p60 /int t10 int m u x 0 1 clk clk clk clk p p p p r r r r c l l l l c c c q q q q q q q q d d d d _ _ _ _ *pull - high (down), open - drain are not shown in the figure. fig. 7 the circuit of i/o port and i/o control register for p60(/int)
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 16 pcrd pcwr pdwr pdrd tin iod p61~p67 port 0 1 m u x clk clk clk p p p l l l r r r c c c d d d q q q q q q _ _ _ *pull - high (down), open - drain are not shown in the figure. fig. 8 the circuit of i/o port and i/o control register for p61~p67 /slep t17 t10 t11 ioce.1 interrupt eni instruction disi instruction interrupt (wake-up from sleep) next instruction (wake-up from sleep) clk clk clk q q q q q q _ _ _ d d d p p p l l l r r r c c c re.1 fig. 9 block diagram of i/o port 6 with input change interrupt/wake - up
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 17 table 2 usage of port 6 input change wake - up/interrupt function usage of port 6 input status change wake - up/interrupt (i) wake - up fr om port 6 input status change (ii) port 6 input status change interrupt (a) before sleep 1. read i/o port 6 (mov r6,r6) 1. disable wdt 2. execute "eni" 2. read i/o port 6 (mov r6,r6) 3. enable interrupt (set iocf.1) 3. execute "eni " or "disi" 4. if port 6 change (interrupt) 4. enable interrupt (set iocf.1) ? interrupt vector (008h) 5. execute "slep" instruction (b) after wake - up 1. if "eni" ? interrupt vector (008h) 2. if "disi" ? next instruction 4 .5 reset and wake - up 1. reset a reset is initiated by (1) power on reset. (2) /reset pin input "low", or (3) wdt time - out (if enabled). the device is kept in a reset condition for a period of approx. 18ms 1 (one oscillator start - up timer peri od) after the reset is detected. once the reset occurs, the following functions are performed. refer to fig.9. ? the oscillator is running, or will be started. ? the program counter (r2) is set to all "0". ? all i/o port pins are configured as input mode ( high - impedance state). ? the watchdog timer and prescaler are cleared. ? when power is switched on, the upper 3 bits of r3 are cleared. ? the bits of the cont register are set to all "1" except for the bit 6 (int flag). ? the bits of the iocb register are set to all "1". ? the iocc register is cleared. ? the bits of the iocd register are set to all "1". ? bit 7 of the ioce register is set to "1", and 6 is cleared. ? bits 0~2 of rf and bits 0~2 of iocf register are cleared. 1 : vdd = 5v, set up time period = 16.5ms 5% vdd = 3v, set up time period = 18ms 5%
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 18 the sleep (power down) mode is att ained by executing the ?slep? instruction. while entering sleep mode, wdt (if enabled) is cleared but keeps on running. the controller can be awakened by (1) external reset input on /reset pin, (2) wdt time - out (if enabled), or (3) port 6 input status chan ges (if enabled). the first two cases will cause the EM78P153E to reset. the t and p flags of r3 can be used to determine the source of the reset (wake - up). the last case is considered the continuation of program execution and the global interrupt ("eni" o r "disi" being executed) decides whether or not the controller branches to the interrupt vector following wake - up. if eni is executed before slep, the instruction will begin to execute from the address 008h after wake - up. if disi is executed before slep, t he operation will restart from the instruction right next to slep after wake - up. only one of cases 2 and 3 can be enabled before entering the sleep mode. that is, [a] if port 6 input status changed interrupt is enabled before slep , wdt must be disabled. b y software. however, the wdt bit in the option register remains enabled. hence, the EM78P153E can be awakened only by case 1 or 3. [b] if wdt is enabled before slep, port 6 input status change interrupt must be disabled. hence, the EM78P153E can be awakene d only by case 1 or 2. refer to the section on interrupt. if port 6 input status change interrupt is used to wake - up the EM78P153E (case [a] above), the following instructions must be executed before slep: mov a, @xxxx1110b ; select wdt prescaler contw wdtc ; clear wdt and prescaler mov a, @0xxxxxxxb ; disable wdt iow re mov r6, r6 ; read port 6 mov a, @00000x1xb ; enable port 6 input change interrupt iow rf eni (or disi) ; enable (or disable) global interrupt slep ; sleep one problem user shou ld be aware of, is that after waking up from the sleep mode, wdt will enable automatically. the wdt operation (being enabled or disabled) should be handled appropriately by software after waking up from sleep mode.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 19 table 3 the summ ary of the initialized values for registers address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name x x x x c53 c52 c51 c50 power - on 0 0 0 0 1 1 1 1 /reset and wdt 0 0 0 0 1 1 1 1 n/a ioc5 wake - up from pin change 0 0 0 0 p p p p bit name c67 c66 c65 c64 c63 c62 c61 c60 power - on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n/a ioc6 wake - up from pin change p p p p p p p p bit name x x x x p53 p52 p51 p50 power - on 1 1 1 1 1 1 1 1 /reset and wdt p p p p p p p p 0x05 p5 wake - up from pin change p p p p p p p p bit name p67 p66 p65 p64 p63 p62 p61 p60 power - on 1 1 1 1 1 1 1 1 /reset and wdt p p p p p p p p 0x06 p6 wake - up from pin change p p p p p p p p bit name x /int ts te pab psr2 psr1 psr 0 power - on 0 0 1 1 1 1 1 1 /reset and wdt 0 0 1 1 1 1 1 1 n/a cont wake - up from pin change 0 p p p p p p p bit name - - - - - - - - power - on u u u u u u u u /reset and wdt p p p p p p p p 0x00 r0(iar) wake - up from pin change p p p p p p p p bit name - - - - - - - - power - on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x01 r1(tcc) wake - up from pin change p p p p p p p p bit name - - - - - - - - power - on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x02 r2(pc) wake - up fr om pin change *p *p *p *p *p *p *p *p bit name rst gp1 gp0 t p z dc c power - on 0 u u 1 1 u u u /reset and wdt 0 p p t t p p p 0x03 r3(sr) wake - up from pin change 1 p p t t p p p bit name gp2 gp1 gp0 - - - - - power - on u u u u u u u u /reset and wdt p p p p p p p p 0x04 r4(rsr) wake - up from pin change p p p p p p p p bit name x x x x x exif icif tcif power - on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x0f rf(isr) wake - up from pin change 0 0 0 0 0 p p p bit name x /pd6 /pd5 /pd4 x /pd2 /pd1 /pd0 0x0b iocb power - on 1 1 1 1 1 1 1 1
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 20 address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 /reset and wdt 1 1 1 1 1 1 1 1 wake - up from pin change p p p p p p p p bit name od7 od6 od5 od4 x od2 od1 od0 power - on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0x0c iocc wak e - up from pin change p p p p p p p p bit name /ph7 /ph6 /ph5 /ph4 x /ph2 /ph1 /ph0 power - on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0x0d iocd wake - up from pin change p p p p p p p p bit name wdte eis x x x x x x power - on 1 0 1 1 1 1 1 1 /reset and wdt 1 0 1 1 1 1 1 1 0x0e ioce wake - up from pin change p p 1 1 1 1 1 1 bit name x x x x x exie icie tcie power - on 1 1 1 1 1 0 0 0 /reset and wdt 1 1 1 1 1 0 0 0 0x0f iocf wake - up from pin change 1 1 1 1 1 p p p bit name - - - - - - - - power - on u u u u u u u u /reset and wdt p p p p p p p p 0x10~0x2f r10~r2 f wake - up from pin change p p p p p p p p x: not used. u: unknown or don?t care. p: previous value before reset. t: check table 4 2. /reset configure refer to fig. 10 when the reset bit in the option word is programmed to 0, the external /reset is enabled. when programmed to 1, the internal /reset is enabled, tied to the internal vdd and the pin is defined as p63. 3. the status of rst, t, and p of status regist er a reset condition is initiated by the following events: 1. a power - on condition, 2. a high - low - high pulse on /reset pin, and 3. watchdog timer time - out. the values of rst, t, and p, listed in table 4 are used to check how the processor wakes up. table 5 shows the events which may affect the status of rst, t, and p.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 21 table 4 the values of rst, t and p after reset reset type rst t p power on 0 1 1 /reset during operating mode 0 *p *p /reset wake - up during sleep mode 0 1 0 wdt du ring operating mode 0 0 p wdt wake - up during sleep mode 0 0 0 wake - up on pin change during sleep mode 1 1 0 *p: previous status before reset table 5 the status of rst, t and p being affected by events. event rst t p power on 0 1 1 wdtc instruction *p 1 1 wdt time - out 0 0 *p slep instruction *p 1 0 wake - up on pin change during sleep mode 1 1 0 *p: previous value before reset voltage detector power-on reset wdte setup time vdd d q clk clr clk reset wdt timeout wdt /reset oscillator fig. 10 block diagram of controller reset
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 22 4 .6 interr upt the EM78P153E has three falling - edge interrupts as listed below: ( 1) tcc overflow interrupt (2) port 6 input status change interrupt (3) external interrupt [(p60, /int) pin]. before the port 6 input status changed interrupt is enabled, reading port 6 ( e.g. "mov r6,r6") is necessary. each pin of port 6 will have this feature if its status changes. any pin configured as output or p60 pin configured as /int, is excluded from this function. the port 6 input status changed interrupt can wake up the EM78P153E from sleep mode if port 6 is enabled prior to going into the sleep mode by executing slep instruction. when the chip wakes - up, the controller will continue to execute the program in - line if the global interrupt is disabled. if the global interrupt is enab led, it will branch to the interrupt vector 008h. rf is the interrupt status register that records the interrupt requests in the relative flags/bits. iocf is an interrupt mask register. the global interrupt is enabled by the eni instruction and is disabled by the disi instruction. when one of the interrupts (enabled) occurs, the next instruction will be fetched from address 008h. once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in rf. the interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and before interrupts are enabled to avoid recursive interrupts. the flag (except icif bit) in the interrupt status register (rf) is set regardless of the status of its mask bit or the execution of eni. note that the outcome of rf will be the logic and of rf and iocf (refer to fig. 11). the reti instruction ends the interrupt routine and enables the global interrupt (the execution of eni). when an interrupt is generated b y the int instruction (enabled), the next instruction will be fetched from address 001h.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 23 int eni/disi iod rfwr iocfrd iocfwr irqn irqm rfrd iocf /reset /irqn vcc rf clk clk q q d p r l c _ p r l c q q _ d fig. 11 interrupt input circuit 4 .7 oscillator 1. oscillator modes the EM78P153E can be operated in four different osc illator modes, such as internal rc oscillator mode (irc), external rc oscillator mode (erc), high xtal oscillator mode(hxt), and low xtal oscillator mode(lxt). user can select one of them by programming ocs1 and osc2 in the code option register. table 6 de picts how these four modes are defined. the up - limited operation frequency of crystal/resonator on the different vdds is listed in table 7. table 6 oscillator modes defined by osc1 and osc2 mode osc1 osc2 irc(internal rc oscillator mode) 1 1 erc(external rc oscillator mode) 1 0 hxt(high xtal oscillator mode) 0 1 lxt(low xtal oscillator mode) 0 0 the transient point of system frequency between hxt and lxy is around 400 khz.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 24 table 7 the summary of m aximum operating speeds conditions vdd fxt max.(mhz) 2.3 4.0 3.0 8.0 two cycles with two clocks 5.0 20.0 2. crystal oscillator/ceramic resonators(xtal) EM78P153E can be driven by an external clock signal through the osci pin as shown in fig. 12. osci osco EM78P153E ext. clock fig. 12 circuit for external clock input in most applications, pin osci and pin osco can be connected with a crystal or ceramic resonator to generate oscillation. fig. 13 depicts such circuit. the same thing ap plies whether it is in the hxt mode or in the lxt mode. table 8 provides the recommended values of c1 and c2. since each resonator has its own attribute, user should refer to its specification for appropriate values of c1 and c2. rs, a serial resistor, may be necessary for at strip cut crystal or low frequency mode. osci osco EM78P153E c1 c2 xtal rs fig. 13 circuit for crystal/resonator
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 25 table 8 capacitor selection guide for crystal oscillator or ceramic resonator os cillator type frequency mode frequency c1(pf) c2(pf) 455 khz 100~150 100~150 2.0 mhz 20~40 20~40 ceramic resonators hxt 4.0 mhz 10~30 10~30 32.768khz 25 15 100khz 25 25 lxt 200khz 25 25 455khz 20~40 20~150 1.0mhz 1 5~30 15~30 2.0mhz 15 15 crystal oscillator hxt 4.0mhz 15 15 EM78P153E osci 7404 x t 7404 7404 330 330 c fig. 14 circuit for crystal/resonator - series mode EM78P153E osci 7404 7404 x t c 1 c 2 10k 4.7k vdd 10k 10k fig. 15 circuit for crystal/resonator - parallel mode
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 26 3. extern al rc oscillator mode for some applications that do not need to have its timing to be calculated precisely, the rc oscillator (fig. 16) offers a lot of cost savings. nevertheless, it should be noted that the frequency of the rc oscillator is influenced by the supply voltage, the values of the resistor (rext), the capacitor (cext), and even the operation temperature. moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation. in order to maintain a stabl e system frequency, the values of the cext should not be less than 20pf, and that the value of rext should not be greater than 1 m ohm. if they cannot be kept in this range, the frequency is easily affected by noise, humidity, and leakage. the smaller the rext in the rc oscillator, the faster its frequency will be. on the contrary, for very low rext values, for instance, 1 k w , the oscillator becomes unstable because the nmos cannot discharge the current of the capacitance correctly. based on the reasons abo ve, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the rc oscillator, the package types, the way the pcb is layout, will affect the system frequency. osci EM78P153E vcc rext cext fig. 16 circuit for external rc oscillator mode
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 27 table 9 rc oscillator frequencies cext rext average fosc 5v,25 c average fosc 3v,25 c 3.3k 3.92 mhz 3.63 mhz 5.1k 2.67 mhz 2.6 mhz 10k 1.4mhz 1.4 mhz 20 pf 100k 150 khz 156 kh z 3.3k 1.4 mhz 1.33 mhz 5.1k 940 khz 917 khz 10k 476 khz 480 khz 100 pf 100k 50khz 52 khz 3.3k 595 khz 570 khz 5.1k 400 khz 384 khz 10k 200 khz 203 khz 300 pf 100k 20.9 khz 20 khz 1. measured on dip packages. 2. design reference o nly. 4. internal rc oscillator mode EM78P153E offers a versatile internal rc mode with default frequency value of 4mhz. internal rc oscillator mode has other frequencies (1mhz, and 455khz) that can be set by option bits, rcm1 and rcm0. all these four main frequencies can be calibrated by programming the option bits, cal0~cal2. table 10 describes a typical instance of the calibration. table 10 calibration selection for internal rc mode c2 c1 c0 *cycle time (ns) *frequency (mhz) 1 0 1 200.4 4.99 1 0 0 211.9 4.72 0 0 1 223.7 4.47 0 0 0 236.4 4.23 1 1 1 250.0 4.00 1 1 0 264.6 3.78 0 1 1 279.3 3.58 0 1 0 295.0 3.39 *:theoretical values, for reference only. it depend on process. 4. 8 code option register the EM78P153E has one code o ption word that is not a part of the normal program memory. the option bits cannot be accessed during normal program execution. code option register and customer id register arrangement distribution:
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 28 word 0 word1 word 2 bit12~bit0 bit1~bit0 bit12~bit0 co de option register (word 0) word 0 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 12 11 10 9 8 7 6 5 4 3 2 1 0 /reset /enwdt clks osc1 ocs0 cs sut1 sut0 type rcout c2 c1 c0 ? bit 12 (/reset ): define pin7 as a reset pin. 0: /reset e nable 1: /reset disable ? bit 11 (/enwtd ): watchdog timer enable bit. 0: enable 1: disable ? bit 10 (clks) : instruction period option bit. 0: two oscillator periods. 1: four oscillator periods. refer to the section of instruction set. ? bit 9 and bit 8 (os c1 and osc0 ) : oscillator modes selection bits. table 11 oscillator modes defined by osc1 and osc0 mode osc1 osc0 irc(internal rc oscillator mode) 1 1 erc(external rc oscillator mode) 1 0 hxt(high xtal oscillator mode) 0 1 lxt(l ow xtal oscillator mode) 0 0 : the transient point of system frequency between hxt and lxy is around 400 khz. ? bit 7 (cs) : code security bit 0: security on 1: security off ? bit6 and bit5 (sut1 and sut0 ) : set - up time of device bits. table 12 set - up time of device programming sut1 sut0 *set - up time 1 1 18 ms 1 0 4.5 ms 0 1 288 ms 0 0 72 ms *:the theoretical values are for reference only.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 29 : rc mode set - up time always 135ns. ? bit 4 (type) : reserved. the bit4 set t o ?0? all the time. ? bit 3 (rcout) : a selecting bit of high or low frequency for internal rc oscillator. rcout pin function 0 p64 1 osco ? bit 2, bit 1, and bit 0 ( cal2, cal1, cal 0 ): calibrator of internal rc mode bit 3 table 13 calibration selection for internal rc mode c2 c1 c0 *cycle time (ns) *frequency (mhz) 1 0 1 200.4 4.99 1 0 0 211.9 4.72 0 0 1 223.7 4.47 0 0 0 236.4 4.23 1 1 1 250.0 4.00 1 1 0 264.6 3.78 0 1 1 279.3 3.58 0 1 0 295.0 3.39 *: 1. theoretical val ues, an instance of the high frequency mode, are shown for reference only, it depend on process. 2. similar way of calculation is also applicable for low frequency mode. 3. code option register (word 1) word1 bit1 bit0 1 0 rcm1 rcm0 bit 1, and bit 0 ( rcm1, rcm0): rc mode selection bits rcm 1 rcm 0 *frequency(mhz) 1 1 4 0 1 1 0 0 455khz 4. customer id register (word 2) bit 12~bit 0 xxxxxxxxxxxxx bit 12~ 0 : customer?s id code 4 .9 power on considerations any microcontroller is not g uaranteed to start to operate properly before the power supply stays at its steady state.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 30 EM78P153E is equipped with power on voltage detector (povd) with a detecting level of 2.0 v. the extra external reset circuit will work well if vdd rises quick enough (50 ms or less). in many critical applications however, extra devices are still required to assist in solving power - up problems. 4 .10 programmable oscillator set - up time the option word contains sut0 and sut1, which can be used to define the oscillator se t up time. theoretically, the range is from 4.5 ms to 72 ms. for most of crystal or ceramic resonators, the lower the operation frequency is, the longer the set - up time may be required. table 12 describes the values of oscillator set - up time. 4 .11 external power 0n reset circuit the circuit shown in fig 17 implements an external rc to produce the reset pulse. the pulse width (time constant) should be kept long enough for vdd to reach minimum operation voltage. this circuit is used when the power supply has slow rise time. because the current leakage from the /reset pin is about 5 m a, it is recommended that r should not be great than 40 k. in this way, the voltage in pin /reset will be held below 0.2v. the diode (d) acts as a short circuit at the moment of po wer down. the capacitor c, will discharged rapidly and fully. rl, the current - limited resistor, will prevent high current discharge or esd (electrostatic discharge) from flowing to pin /reset. EM78P153E /reset vdd d r rin c fig. 17 extern al power - up reset circuit 4 .12 residue - voltage protection when battery is replaced, device power (vdd) is taken off but residue - voltage remains. the residue - voltage may trips below vdd minimum, but not to zero. this condition may cause a poor power
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 31 on rese t. fig.18 and fig. 19 show how to build a residue - voltage protection circuit. EM78P153E /reset vdd 100k q1 1n4684 10k 33k vdd fig. 18 circuit 1 for the residue voltage protection EM78P153E /reset vdd q1 vdd r3 r2 r1 fig. 19 circuit 2 for the r esidue voltage protection 4 .13 instruction set each instruction in the instruction set is a 13 - bit word divided into an op code and one or more operands. normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction "mov r2,a", "add r2,a", or by instructions of arithmetic or logic operation on r2 (e.g. "sub r2,a", "bs(c) r2,6", "clr r2", ). in this case, the execution takes two instruc tion cycles. if for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows: (a) modify one instruction cycle to consist of 4 oscillator periods.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 32 (b) execute within two in struction cycles the "jmp", "call", "ret", "retl", "reti" commands, or the conditional skip ("jbs", "jbc", "jz", "jza", "djz", "djza") which were tested to be true. the instructions that are written to the program counter, should also take two instruction cycles. the case (a) is selected by the code option bit, called clk. one instruction cycle will consist of two oscillator clocks if clk is low, and four oscillator clocks if clk is high. the case (b) is selected by another code option bit, called cyes. exe cution of the instructions listed in case (b) takes one instruction cycle if cyes is low, and takes two instruction cycles if cyes is high. case (a) and case (b) are independent options, that is, they can be selected separately. note that once the 4 oscill ator periods within one instruction cycle is selected under case (a), the internal clock source to tcc will be clk=fosc/4 (not fosc/ 2) as illustrated in fig. 5. in addition, the instruction set has the following features: (1) every bit of any register can be set, cleared, or tested directly. (2) the i/o register can be regarded as general register. that is, the same instruction can operate on i/o register. the symbol "r" represents a register designator that specifies which one of the registers (including operational registers and general purpose registers) is to be utilized by the instruction. "b" represents a bit field designator that selects the value for the bit which is located in the register "r", and affects the operation. "k" represents an 8 or 10 - bit constant or literal value. instruction binary hex mnemonic operation status affected 0 0000 0000 0000 0000 nop no operation none 0 0000 0000 0001 0001 daa decimal adjust a c 0 0000 0000 0010 0002 contw a ? cont none 0 0000 0000 0011 00 03 slep 0 ? wdt, stop oscillator t,p 0 0000 0000 0100 0004 wdtc 0 ? wdt t,p 0 0000 0000 rrrr 000r iow r a ? iocr none 0 0000 0001 0000 0010 eni enable interrupt none 0 0000 0001 0001 0011 disi disable interrupt none 0 0000 0001 0010 0012 ret [top of stack] ? pc none 0 0000 0001 0011 0013 reti [top of stack] ? pc, enable interrupt none 0 0000 0001 0100 0014 contr cont ? a none 0 0000 0001 rrrr 001r ior r iocr ? a none 0 0000 01rr rrrr 00rr mov r,a a ? r none 0 0000 1000 0000 0080 clra 0 ? a z 0 0000 11rr rrrr 00rr clr r 0 ? r z 0 0001 00rr rrrr 01rr sub a,r r - a ? a z,c,dc 0 0001 01rr rrrr 01rr sub r,a r - a ? r z,c,dc 0 0001 10rr rrrr 01rr deca r r - 1 ? a z 0 0001 11rr rrrr 01rr dec r r - 1 ? r z 0 0010 00rr rrrr 02rr or a,r a v r ? a z
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 33 0 0010 01rr rrrr 02rr or r,a a v r ? r z 0 0010 10rr rrrr 02rr and a,r a & r ? a z 0 0010 11rr rrrr 02rr and r,a a & r ? r z 0 0011 00rr rrrr 03rr xor a,r a ? r ? a z 0 0 011 01rr rrrr 03rr xor r,a a ? r ? r z 0 0011 10rr rrrr 03rr add a,r a + r ? a z,c,dc 0 0011 11rr rrrr 03rr add r,a a + r ? r z,c,dc 0 0100 00rr rrrr 04rr mov a,r r ? a z 0 0100 01rr rrrr 04rr mov r,r r ? r z 0 0100 10rr rrrr 04 rr coma r /r ? a z 0 0100 11rr rrrr 04rr com r /r ? r z 0 0101 00rr rrrr 05rr inca r r+1 ? a z 0 0101 01rr rrrr 05rr inc r r+1 ? r z 0 0101 10rr rrrr 05rr djza r r - 1 ? a, skip if zero none 0 0101 11rr rrrr 05rr djz r r - 1 ? r, skip if zero none 0 0110 00rr rrrr 06rr rrca r r(n) ? a(n - 1), r(0) ? c, c ? a(7) c 0 0110 01rr rrrr 06rr rrc r r(n) ? r(n - 1), r(0) ? c, c ? r(7) c 0 0110 10rr rrrr 06rr rlca r r(n) ? a(n+1), r(7) ? c, c ? a(0) c 0 0110 11rr rrrr 06rr rlc r r (n) ? r(n+1), r(7) ? c, c ? r(0) c 0 0111 00rr rrrr 07rr swapa r r(0 - 3) ? a(4 - 7), r(4 - 7) ? a(0 - 3) none 0 0111 01rr rrrr 07rr swap r r(0 - 3) ? r(4 - 7) none 0 0111 10rr rrrr 07rr jza r r+1 ? a, skip if zero none 0 0111 11rr rrrr 07rr jz r r +1 ? r, skip if zero none 0 100b bbrr rrrr 0xxx bc r,b 0 ? r(b) none 0 101b bbrr rrrr 0xxx bs r,b 1 ? r(b) none 0 110b bbrr rrrr 0xxx jbc r,b if r(b)=0, skip none 0 111b bbrr rrrr 0xxx jbs r,b if r(b)=1, skip none 1 00kk kkkk kkkk 1kkk call k pc+1 ? [sp], (page, k) ? pc none 1 01kk kkkk kkkk 1kkk jmp k (page, k) ? pc none 1 1000 kkkk kkkk 18kk mov a,k k ? a none 1 1001 kkkk kkkk 19kk or a,k a k ? a z 1 1010 kkkk kkkk 1akk and a,k a & k ? a z 1 10 11 kkkk kkkk 1bkk xor a,k a ? k ? a z 1 1100 kkkk kkkk 1ckk retl k k ? a, [top of stack] ? pc none 1 1101 kkkk kkkk 1dkk sub a,k k - a ? a z,c,dc 1 1110 0000 0001 1e01 int pc+1 ? [sp], 001h ? pc none 1 1111 kkkk kkkk 1fkk add a,k k+a ? a z, c,dc this instruction is applicable to ioc5~ioc6, iocb~iocf only. this instruction is not recommended for rf operation. this instruction cannot operate under rf.
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 34 4 .14 timing diagram reset timing (clk="0") clk /reset nop instruction 1 executed tdrh tcc input timing (clks="0") clk tcc ttcc tins ac testing : input is driven at 2.4v for logic "1",and 0.4v for logic "0".timing measurements are made at 2.0v for logic "1",and 0.8v for logic "0". ac test input/output waveform 2.4 0.4 2.0 0.8 test points 2.0 0.8
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 35 5 . absolute maxi munm ratings items rating temperature under bias 0 c to 70 c storage temperature - 65 c to 150 c input voltage - 0.3v to +6.0v output voltage - 0.3v to +6.0v
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 36 6 . electrical characteristic 6.1 dc electrical characteristic ( ta= 0 c ~ 70 c, vdd= 5.0v 5%, vss= 0v ) symbol parameter condition min typ. max unit xtal: vdd to 3v two cycle with two clocks dc 8.0 mhz fxt xtal: vdd to 5v two cycle with two clocks dc 20.0 mhz erc erc: vdd to 5v r: 5k w , c: 39 pf f 20 % 602 f 20 % khz iil input leakage current for input pins vin = vdd, vss 1 m a vih1 input high voltage (vdd=5.0v) ports 5, 6 2.0 v vil1 input low voltage (vdd=5.0v) ports 5, 6 0.8 v viht1 input high threshold voltage (vdd=5.0v) /reset, tcc 2.0 v vilt1 input low threshold voltage (vdd=5. 0v) /reset, tcc 0.8 v vihx1 clock input high voltage vdd=5.0v) osci 2.5 v vilx1 clock input low voltage(vdd=5.0v) osci 1.0 v vih2 input high voltage (vdd=3v) ports 5, 6 1.5 v vil2 input low voltage (vdd=3v) ports 5, 6 0.4 v viht2 input high threshold voltage (vdd=3v) /reset, tcc 1.5 v vilt2 input low threshold voltage (vdd=3v) /reset, tcc 0.4 v vihx2 clock input high voltage (vdd=3v) osci 1.5 v vilx2 clock input low voltage (vdd=3v) osci 0.6 v voh1 output high voltage (ports 5, 6) ioh = - 12.0 ma 2.4 v vol1 output low voltage (p50~p53, p60~p63, p66~p67) iol = 12.0 ma 0.4 v vol2 output low voltage (p64,p65) iol = 16.0 ma 0.4 v iph pull - high current pull - high active, input pin at vss - 50 - 100 - 240 m a ipd pull - down current pu ll - down active, input pin at vdd 25 50 120 m a isb 2 power down current all input and i/o pins at vdd, output pin floating, wdt enabled 4 m a isb 1 power down current all input and i/o pins at vdd, output pin floating, wdt disabled 1 m a icc1 operating s upply current (vdd=3v) at two cycles/four clocks /reset= 'high', fosc=32khz (crystal type,clk="0"), output pin floating, wdt disabled 15 15 30 m a icc2 operating supply current (vdd=3v) at two cycles/four clocks /reset= 'high', fosc=32khz (crystal type,clk ="0"), output pin floating, wdt enabled 19 35 m a icc3 operating supply current (vdd=5.0v) at two cycles/two clocks /reset= 'high', fosc=2mhz (crystal type, clk="0"), output pin floating 2.0 ma icc4 operating supply current (vdd=5.0v) at two cycles/fou r clocks /reset= 'high', fosc=4mhz (crystal type, clk="0"), output pin floating 4.0 ma
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 37 6 .2 ac electrical characteristic (ta=0 c ~ 70 c, vdd=5v 5%, vss=0v) symbol parameter conditions min typ max unit dclk input clk duty cycle 45 50 55 % crystal type 100 dc ns tins instru ction cycle time (clk="0") rc type 500 dc ns ttcc tcc input period (tins+20)/n* ns tdrh device reset hold time ta = 25 c 9 18 30 ms trst /reset pulse width ta = 25 c 2000 ns twdt watchdog timer period ta = 25 c 4.5 18 7 2 ms tset input pin setup time 0 ms thold input pin hold time 20 ms tdelay output pin delay time cload=20pf 50 ms * n= selected prescaler ratio. * the duration of watch dog timer is determined by option code (bit6, bit5).
EM78P153E otp rom this specification is subject to change without prior notice. 2002/03/01 38 appendix package typ es: otp mcu package type pin count package size EM78P153Ep dip 14 300 mil EM78P153En sop 14 150 mil

▲Up To Search▲

Price & Availability of EM78P153E

	To Download EM78P153E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .